The present invention relates to a data memory capable of reading and writing simultaneously in one memory cycle and capable of sequentially reading out written information in the order the data is received, i.e., such that the first written information is read first.
In the past, such data memories were formed, in many cases, of flip-flops (FF's) or latches including combinations of gates, or conventional memory cells (which allow one read or write operation in each memory cycle). The former is sufficiently fast but a huge number of gates are required to construct a large capacity data memory of such a kind. The conventional memory cells, on the other hand, need two memory cycles for writing and reading data. The speed of such memory cells is not compatible with the presently available pipelining techniques. On the other hand, it is difficult to obtain memory cells for a large capacity memory which can execute one memory cycle in one half of the pitch time of the pipeline data processor.